Asynchronous microprocessors: From high level model to FPGA implementation

In order to determine the applicability of both programmable software tools and pro-grammable hardware for asynchronous logic applications an implementation, employing FPGA devices, of the instruction decode and the instruction execution stages of an asyn-chronous microprocessor, the ADLX, is presented. The foundation for that microprocessor is based on the employment of event driven logic, speciically 2-phase transition signalling, that functions within the conceptual framework of a Sutherland micropipeline. The entire design has been constructed from a series of VHDL descriptions that have been compiled and simulated using both the Cypress WARP VHDL Development System and the AMD MACHXL software packages. A number of the asynchronous speciic areas of the ADLX have been synthesized using Petrify, a Petri Net tool designed for the manipulation of concurrent speciications of asynchronous control circuits. The ADLX itself has been constructed from a range of \oo-the-shelf" products including HM 65764 high speed CMOS SRAM semiconductors and FPGA logic devices.